As conventional vertical DRAM cells are scaled below a design groundrule of about 110 nm, encroachment of the buried-strap region upon the sidewall of the adjacent storage trench cuts-off the path holes flowing into and out of the portion of the P-well above the buried-strap region.
Simulation has demonstrated that floating-well effects limit the scalability of prior art vertical DRAM memory arrays to a minimum distance of about 90 nm between adjacent storage trenches. A number of dynamic leakage mechanisms limiting the scalability of conventional vertical DRAM memory cells have been identified and quantified. Included in the dynamic leakage mechanisms are: (1) Floating-well bitline disturb (FWBD), (2) Transient drain induced barrier lowering (TDIBL), and (3) Adjacent wordline induced punchthrough (AWIPT).
The onset of serious charge loss due to each mechanism occurs at approximately 90 nm end of process deep trench (DT) to deep trench (DT) spacing. Thus, scalability of conventional vertical DRAM memory cells beyond 110 nm is expected to be limited by floating-well effects.
An illustration of a dominant floating-well dynamic leakage mechanism that limits scalability of prior art vertical DRAM memory arrays is shown in FIG. 1. Specifically, at a time indicated by point A of FIG. 1 and during a long period of about 5-100 ns of repeated writing of a "1" to other memory cells on the bitline, the P-well of an unselected cell storing a "1" may leak up towards V.sub.b1h, as the exiting of holes is restricted by parasitic JFET. Leakage depends on the degree of well isolation caused by pinchoff from expansion of the storage node depletion region. In an extreme case, the buried-strap region may come in contact with the adjacent deep trench capacitor. Moreover, the hole current through the pinchoff region must keep up with the leakage to avoid a pseudo "Floating-Body Effect".
Insofar as time interval B-C is concerned, the N+ bitline diffusion to P-well barrier is lowered by a downward swing of V.sub.b1h. Electrons emitted from the bitline diffusion region are collected by the storage node resulting in the formation of a parasitic bipolar transistor, Q.sub.B, (PW.sub.int is a floating base) within the memory cell array.
For aggressively scaled vertical metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM memory cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in "Floating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)", Proceedings, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, October 1996.
An illustration of the storage capacitor voltage vs. the voltage in the portion of the P-well isolated by the depletion region from the buried-strap outdiffusion, as the bitline is cycled, is shown in FIG. 2. When the bitline is held at V.sub.b1h, the isolation portion of the P-well leaks up towards the voltage of the adjacent diffusions. With subsequent cycling of the bitline between 0.0 and V.sub.b1h, the dynamic charge loss mechanism results in charge pumping which discharges the storage capacitor. Between data refresh, greater than 10.sup.6 bitline cycles are possible, which is sufficient to discharge the storage capacitor.
One possible solution to the scalability limitation resulting from floating-well effects, which has not yet been implemented in existing memory structures, includes a contact to the portion of the P-well above the buried-strap outdiffusion region. If such a memory structure is possible, it must be provided in a manner that does not negatively impact cell density, does not degrade junction leakage, and does not add to the fabrication complexity. To date, applicants are unaware of a prior art vertical DRAM memory structure of this type that overcomes the scalability limitation resulting from floating-well effects.
The present invention provides a processing scheme which provides a contacted body and maintains low junction leakage, while actually reducing fabrication cost, retarding the onset of scalability limitations due to floating-well effects to approximately 60 nm groundrules.